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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[20]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[20]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[20]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[20]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[20]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[20]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[20]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[20]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[20]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[20]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[20]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[20]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[19]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[19]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[19]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[19]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[19]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[19]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[19]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[19]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[19]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[19]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[19]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[19]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[19]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[18]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[18]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[18]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[18]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[18]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[18]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[18]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[18]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[18]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[18]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[18]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[18]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[18]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[17]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[17]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[17]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[17]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[17]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[17]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[17]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[17]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[17]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[17]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[17]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[17]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[17]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[16]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[16]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[16]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[16]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[16]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[16]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[16]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[16]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[16]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[16]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[16]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[16]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[16]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[15]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[15]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[15]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[15]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[15]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[15]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[15]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[15]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[15]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[15]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[15]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[15]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[15]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[14]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[14]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[14]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[14]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[14]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[14]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[14]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[14]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[14]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[14]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[14]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[14]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[14]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[13]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[13]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[13]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[13]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[13]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[13]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[13]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[13]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[13]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[13]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[13]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[13]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[13]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[12]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[12]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[12]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[12]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[12]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[12]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[12]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[12]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[12]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[12]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[12]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[12]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[12]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[11]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[11]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[11]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[11]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[11]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[11]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[11]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[11]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[11]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[11]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[11]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[11]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[11]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[10]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[10]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[10]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[10]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[10]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[10]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[10]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[10]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[10]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[10]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[10]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[10]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[10]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[9]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[9]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[9]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[9]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[9]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[9]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[9]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[9]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[9]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[9]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[9]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[9]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[9]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[8]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[8]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[8]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[8]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[8]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[8]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[8]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[8]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[8]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[8]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[8]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[8]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[8]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[7]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[7]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[7]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[7]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[7]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[7]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[7]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[7]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[7]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[7]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[7]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[7]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[7]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[6]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[6]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[6]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[6]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[6]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[6]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[6]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[6]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[6]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[6]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[6]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[6]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[6]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[5]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[5]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[5]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[5]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[5]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[5]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[5]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[5]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[5]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[5]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[5]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[5]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[5]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[4]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[4]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[4]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[4]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[4]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[4]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[4]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[4]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[4]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[4]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[4]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[4]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[4]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[3]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[3]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[3]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[3]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[3]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[3]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[3]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[3]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[3]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[3]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[3]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[3]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[3]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[2]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[2]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[2]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[2]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[2]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[2]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[2]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[2]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[2]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[2]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[2]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[2]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[2]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[1]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[1]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[1]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[1]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[1]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[1]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[1]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[1]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[1]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[1]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[1]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[1]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[1]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[0]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[0]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[0]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[0]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[0]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[0]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer1/alu_cell[0]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[0]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[0]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[0]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[0]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[0]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer1/alu_cell[0]/z}
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer1/lac/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer1/lac/root/p
add wave -noupdate -format Logic /cpu5_testbench/dut/PC/clk
add wave -noupdate -format Logic /cpu5_testbench/dut/PC/reset
add wave -noupdate -format Literal /cpu5_testbench/dut/PC/in
add wave -noupdate -format Literal /cpu5_testbench/dut/PC/out
add wave -noupdate -format Logic /cpu5_testbench/dut/IFID/clk
add wave -noupdate -format Logic /cpu5_testbench/dut/IFID/reset
add wave -noupdate -format Literal /cpu5_testbench/dut/IFID/in
add wave -noupdate -format Literal /cpu5_testbench/dut/IFID/in2
add wave -noupdate -format Literal /cpu5_testbench/dut/IFID/out
add wave -noupdate -format Literal /cpu5_testbench/dut/IFID/out2
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/out_d
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/Cout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/V
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/a
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/b
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/S
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/shamt
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/d
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/c
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/p
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/bb
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[31]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[31]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[31]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[31]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[31]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[31]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[31]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[31]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[31]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[31]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[31]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[31]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[31]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[30]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[30]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[30]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[30]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[30]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[30]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[30]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[30]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[30]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[30]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[30]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[30]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[30]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[29]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[29]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[29]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[29]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[29]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[29]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[29]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[29]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[29]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[29]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[29]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[29]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[29]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[28]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[28]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[28]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[28]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[28]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[28]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[28]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[28]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[28]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[28]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[28]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[28]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[28]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[27]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[27]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[27]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[27]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[27]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[27]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[27]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[27]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[27]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[27]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[27]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[27]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[27]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[26]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[26]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[26]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[26]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[26]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[26]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[26]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[26]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[26]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[26]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[26]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[26]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[26]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[25]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[25]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[25]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[25]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[25]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[25]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[25]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[25]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[25]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[25]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[25]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[25]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[25]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[24]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[24]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[24]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[24]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[24]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[24]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[24]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[24]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[24]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[24]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[24]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[24]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[24]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[23]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[23]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[23]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[23]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[23]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[23]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[23]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[23]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[23]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[23]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[23]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[23]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[23]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[22]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[22]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[22]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[22]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[22]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[22]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[22]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[22]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[22]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[22]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[22]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[22]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[22]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[21]/d}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[21]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[21]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[21]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[21]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[21]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[21]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[21]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[21]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[21]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[21]/y}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[20]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[20]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[20]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[20]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[20]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[20]/c}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[20]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[20]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[20]/z}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[19]/g}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[19]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[19]/b}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[19]/bint}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[19]/y}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[18]/bint}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[18]/y}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[17]/d}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[17]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[17]/b}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[17]/y}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[16]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[16]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[16]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[16]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[16]/b}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[16]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[16]/bint}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[16]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[16]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[16]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[15]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[15]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[15]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[15]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[15]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[15]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[15]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[15]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[15]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[15]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[15]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[15]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[15]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[14]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[14]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[14]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[14]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[14]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[14]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[14]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[14]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[14]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[14]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[14]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[14]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[14]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[13]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[13]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[13]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[13]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[13]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[13]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[13]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[13]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[13]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[13]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[13]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[13]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[13]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[12]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[12]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[12]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[12]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[12]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[12]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[12]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[12]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[12]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[12]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[12]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[12]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[12]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[11]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[11]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[11]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[11]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[11]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[11]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[11]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[11]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[11]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[11]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[11]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[11]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[11]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[10]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[10]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[10]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[10]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[10]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[10]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[10]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[10]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[10]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[10]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[10]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[10]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[10]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[9]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[9]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[9]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[9]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[9]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[9]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[9]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[9]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[9]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[9]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[9]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[9]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[9]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[8]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[8]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[8]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[8]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[8]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[8]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[8]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[8]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[8]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[8]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[8]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[8]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[8]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[7]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[7]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[7]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[7]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[7]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[7]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[7]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[7]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[7]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[7]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[7]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[7]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[7]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[6]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[6]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[6]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[6]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[6]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[6]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[6]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[6]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[6]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[6]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[6]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[6]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[6]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[5]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[5]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[5]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[5]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[5]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[5]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[5]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[5]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[5]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[5]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[5]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[5]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[5]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[4]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[4]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[4]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[4]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[4]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[4]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[4]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[4]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[4]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[4]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[4]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[4]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[4]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[3]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[3]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[3]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[3]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[3]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[3]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[3]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[3]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[3]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[3]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[3]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[3]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[3]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[2]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[2]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[2]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[2]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[2]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[2]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[2]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[2]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[2]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[2]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[2]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[2]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[2]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[1]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[1]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[1]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[1]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[1]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[1]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[1]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[1]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[1]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[1]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[1]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[1]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[1]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[0]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[0]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[0]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[0]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[0]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[0]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/pcincrementer2/alu_cell[0]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[0]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[0]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[0]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[0]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[0]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/pcincrementer2/alu_cell[0]/z}
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/pcincrementer2/lac/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/pcincrementer2/lac/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/pc_jumpR/in1
add wave -noupdate -format Literal /cpu5_testbench/dut/pc_jumpR/in2
add wave -noupdate -format Literal /cpu5_testbench/dut/pc_jumpR/out
add wave -noupdate -format Logic /cpu5_testbench/dut/pc_jumpR/sel
add wave -noupdate -format Literal /cpu5_testbench/dut/pc_jump/in1
add wave -noupdate -format Literal /cpu5_testbench/dut/pc_jump/in2
add wave -noupdate -format Literal /cpu5_testbench/dut/pc_jump/out
add wave -noupdate -format Logic /cpu5_testbench/dut/pc_jump/sel
add wave -noupdate -format Literal /cpu5_testbench/dut/pcmux/in1
add wave -noupdate -format Literal /cpu5_testbench/dut/pcmux/in2
add wave -noupdate -format Literal /cpu5_testbench/dut/pcmux/out
add wave -noupdate -format Logic /cpu5_testbench/dut/pcmux/sel
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/ibus
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/Aselect
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/Bselect
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/dselect
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/clk
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/imm
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/cint
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/memtoreg
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/memread
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/slt
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/sle
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/sint
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/wire1
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/wire2
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rs/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rs/out
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rs/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rs/dec/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rs/dec/out
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rs/dec1/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rs/dec1/out
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/rs/dec1/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rs/dec2/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rs/dec2/out
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/rs/dec2/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rs/dec3/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rs/dec3/out
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/rs/dec3/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rs/dec4/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rs/dec4/out
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/rs/dec4/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rt/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rt/out
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rt/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rt/dec/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rt/dec/out
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rt/dec1/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rt/dec1/out
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/rt/dec1/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rt/dec2/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rt/dec2/out
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/rt/dec2/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rt/dec3/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rt/dec3/out
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/rt/dec3/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rt/dec4/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rt/dec4/out
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/rt/dec4/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rd/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rd/out
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rd/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rd/dec/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rd/dec/out
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rd/dec1/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rd/dec1/out
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/rd/dec1/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rd/dec2/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rd/dec2/out
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/rd/dec2/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rd/dec3/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rd/dec3/out
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/rd/dec3/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rd/dec4/in
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/rd/dec4/out
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/rd/dec4/en
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/mux1/in1
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/mux1/in2
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/mux1/out
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/mux1/sel
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/opcodedecoder/opcode
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/opcodedecoder/func
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/opcodedecoder/imm
add wave -noupdate -format Logic /cpu5_testbench/dut/controllercpu4/opcodedecoder/cin
add wave -noupdate -format Literal /cpu5_testbench/dut/controllercpu4/opcodedecoder/s
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/clk
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/Cin
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/imm
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/Aselect
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/Bselect
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/Dselect
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/signext
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/mem_dbus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/abus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/bbus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/dbus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/S
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/shamt
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/eq_det_out
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/Cout
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/wiremux0
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/pipedbbus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/wireabus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/pipedabus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/RF/Aselect
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/RF/Bselect
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/RF/Dselect
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/RF/dbus
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/RF/clk
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/RF/abus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/RF/bbus
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/RF/A0/sel
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/RF/A0/bus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/RF/A0/Qi1
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/RF/B0/sel
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/RF/B0/bus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/RF/B0/Qi1
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[31]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[31]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[31]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[31]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[31]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[31]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[31]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[31]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[31]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[30]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[30]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[30]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[30]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[30]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[30]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[30]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[30]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[30]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[29]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[29]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[29]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[29]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[29]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[29]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[29]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[29]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[29]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[28]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[28]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[28]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[28]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[28]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[28]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[28]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[28]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[28]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[27]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[27]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[27]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[27]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[27]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[27]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[27]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[27]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[27]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[26]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[26]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[26]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[26]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[26]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[26]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[26]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[26]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[26]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[25]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[25]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[25]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[25]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[25]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[25]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[25]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[25]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[25]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[24]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[24]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[24]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[24]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[24]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[24]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[24]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[24]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[24]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[23]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[23]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[23]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[23]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[23]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[23]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[23]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[23]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[23]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[22]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[22]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[22]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[22]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[22]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[22]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[22]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[22]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[22]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[21]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[21]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[21]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[21]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[21]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[21]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[21]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[21]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[21]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[20]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[20]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[20]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[20]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[20]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[20]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[20]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[20]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[20]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[19]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[19]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[19]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[19]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[19]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[19]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[19]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[19]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[19]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[18]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[18]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[18]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[18]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[18]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[18]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[18]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[18]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[18]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[17]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[17]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[17]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[17]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[17]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[17]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[17]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[17]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[17]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[16]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[16]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[16]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[16]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[16]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[16]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[16]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[16]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[16]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[15]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/Bselect}
add wave -noupdate -format Literal -radix hexadecimal {/cpu5_testbench/dut/regalucpu4/RF/R[15]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[15]/bbus}
add wave -noupdate -format Literal -radix hexadecimal {/cpu5_testbench/dut/regalucpu4/RF/R[15]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[15]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[15]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[15]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[15]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[15]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[14]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[14]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[14]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[14]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[14]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[14]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[14]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[14]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[14]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[13]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[13]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[13]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[13]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[13]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[13]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[13]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[13]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[13]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[12]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[12]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[12]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[12]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[12]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[12]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[12]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[12]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[12]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[11]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[11]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[11]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[11]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[11]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[11]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[11]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[11]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[11]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[10]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[10]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[10]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[10]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[10]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[10]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[10]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[10]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[10]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[9]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[9]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[9]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[9]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[9]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[9]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[9]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[9]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[9]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[8]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[8]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[8]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[8]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[8]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[8]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[8]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[8]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[8]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[7]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[7]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[7]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[7]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[7]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[7]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[7]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[7]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[7]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[6]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[6]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[6]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[6]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[6]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[6]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[6]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[6]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[6]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[5]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[5]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[5]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[5]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[5]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[5]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[5]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[5]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[5]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[4]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[4]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[4]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[4]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[4]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[4]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[4]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[4]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[4]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[3]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[3]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[3]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[3]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[3]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[3]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[3]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[3]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[3]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[2]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[2]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[2]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[2]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[2]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[2]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[2]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[2]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[2]/X1[0]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/dsel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[1]/dbus}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/Aselect}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/Bselect}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[1]/abus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[1]/bbus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[1]/Qi}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/A/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[1]/A/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[1]/A/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/B/sel}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[1]/B/bus}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/RF/R[1]/B/Qi1}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[31]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[31]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[31]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[31]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[31]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[30]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[30]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[30]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[30]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[30]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[29]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[29]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[29]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[29]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[29]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[28]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[28]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[28]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[28]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[28]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[27]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[27]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[27]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[27]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[27]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[26]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[26]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[26]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[26]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[26]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[25]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[25]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[25]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[25]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[25]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[24]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[24]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[24]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[24]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[24]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[23]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[23]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[23]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[23]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[23]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[22]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[22]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[22]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[22]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[22]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[21]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[21]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[21]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[21]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[21]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[20]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[20]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[20]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[20]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[20]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[19]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[19]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[19]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[19]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[19]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[18]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[18]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[18]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[18]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[18]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[17]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[17]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[17]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[17]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[17]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[16]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[16]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[16]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[16]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[16]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[15]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[15]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[15]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[15]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[15]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[14]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[14]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[14]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[14]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[14]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[13]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[13]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[13]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[13]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[13]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[12]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[12]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[12]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[12]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[12]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[11]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[11]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[11]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[11]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[11]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[10]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[10]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[10]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[10]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[10]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[9]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[9]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[9]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[9]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[9]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[8]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[8]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[8]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[8]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[8]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[7]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[7]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[7]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[7]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[7]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[6]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[6]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[6]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[6]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[6]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[5]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[5]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[5]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[5]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[5]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[4]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[4]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[4]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[4]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[4]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[3]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[3]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[3]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[3]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[3]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[2]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[2]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[2]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[2]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[2]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[1]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[1]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[1]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[1]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[1]/cl}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[0]/D}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[0]/clk}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[0]/dsel}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[0]/Q}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/RF/R[1]/X1[0]/cl}
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/equal_detector/in1
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/equal_detector/in2
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/equal_detector/out
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/equal_detector/clk
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/equal_detector/wire1
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/dbus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/pipedbbus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/pipedabus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/abus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/bbus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/signext
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/Cin
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/clk
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/imm2
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/S
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/shamt
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/Cout
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/d
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/wirepipedbbus
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/qa
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/qb
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/muxb4alu/in1
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/muxb4alu/in2
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/muxb4alu/out
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/muxb4alu/sel
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/ffA/D
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/ffA/Q
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/ffA/clk
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/ffB/D
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/ffB/Q
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/ffB/clk
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/ffD/D
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/ffD/Q
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/ffD/clk
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/out_d
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/Cout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/V
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/a
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/b
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/S
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/shamt
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/d
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/c
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/p
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/bb
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[31]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[31]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[31]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[31]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[31]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[31]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[31]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[31]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[31]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[31]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[31]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[31]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[31]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[30]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[30]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[30]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[30]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[30]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[30]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[30]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[30]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[30]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[30]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[30]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[30]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[30]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[29]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[29]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[29]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[29]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[29]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[29]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[29]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[29]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[29]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[29]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[29]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[29]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[29]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[28]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[28]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[28]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[28]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[28]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[28]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[28]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[28]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[28]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[28]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[28]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[28]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[28]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[27]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[27]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[27]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[27]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[27]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[27]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[27]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[27]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[27]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[27]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[27]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[27]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[27]/z}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[26]/d}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[26]/g}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[26]/p}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[26]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[26]/b}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[26]/c}
add wave -noupdate -format Literal {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[26]/S}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[26]/cint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[26]/bint}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[26]/m}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[26]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[26]/y}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[11]/a}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[11]/b}
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add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[0]/x}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[0]/y}
add wave -noupdate -format Logic {/cpu5_testbench/dut/regalucpu4/A/alu/alu_cell[0]/z}
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/c
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add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/c
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add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/g
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add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf0/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/cint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/gint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/pint
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/leaf0/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/leaf0/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/leaf0/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/leaf0/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/leaf0/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/leaf0/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/leaf1/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/leaf1/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/leaf1/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/leaf1/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/leaf1/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/leaf1/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/leaf1/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/root/c
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/root/gout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/root/pout
add wave -noupdate -format Logic /cpu5_testbench/dut/regalucpu4/A/alu/lac/root/Cin
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/root/g
add wave -noupdate -format Literal /cpu5_testbench/dut/regalucpu4/A/alu/lac/root/p
add wave -noupdate -format Literal /cpu5_testbench/dut/IDEX/in1
add wave -noupdate -format Literal /cpu5_testbench/dut/IDEX/in2
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/in3
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/clk
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/in4
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/in6
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/in8
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/in9
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/in10
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/in11
add wave -noupdate -format Literal /cpu5_testbench/dut/IDEX/in5
add wave -noupdate -format Literal /cpu5_testbench/dut/IDEX/in7
add wave -noupdate -format Literal /cpu5_testbench/dut/IDEX/out1
add wave -noupdate -format Literal /cpu5_testbench/dut/IDEX/out2
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/out3
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/out4
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/out6
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/out8
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/out9
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/out10
add wave -noupdate -format Logic /cpu5_testbench/dut/IDEX/out11
add wave -noupdate -format Literal /cpu5_testbench/dut/IDEX/out5
add wave -noupdate -format Literal /cpu5_testbench/dut/IDEX/out7
add wave -noupdate -format Literal /cpu5_testbench/dut/signextender/in
add wave -noupdate -format Literal /cpu5_testbench/dut/signextender/out
add wave -noupdate -format Literal /cpu5_testbench/dut/EXMEM/in1
add wave -noupdate -format Literal /cpu5_testbench/dut/EXMEM/in3
add wave -noupdate -format Logic /cpu5_testbench/dut/EXMEM/in2
add wave -noupdate -format Logic /cpu5_testbench/dut/EXMEM/in4
add wave -noupdate -format Logic /cpu5_testbench/dut/EXMEM/clk
add wave -noupdate -format Logic /cpu5_testbench/dut/EXMEM/in5
add wave -noupdate -format Logic /cpu5_testbench/dut/EXMEM/in6
add wave -noupdate -format Logic /cpu5_testbench/dut/EXMEM/in7
add wave -noupdate -format Logic /cpu5_testbench/dut/EXMEM/in8
add wave -noupdate -format Literal /cpu5_testbench/dut/EXMEM/out1
add wave -noupdate -format Literal /cpu5_testbench/dut/EXMEM/out3
add wave -noupdate -format Logic /cpu5_testbench/dut/EXMEM/out2
add wave -noupdate -format Logic /cpu5_testbench/dut/EXMEM/out4
add wave -noupdate -format Logic /cpu5_testbench/dut/EXMEM/out5
add wave -noupdate -format Logic /cpu5_testbench/dut/EXMEM/out6
add wave -noupdate -format Logic /cpu5_testbench/dut/EXMEM/out7
add wave -noupdate -format Logic /cpu5_testbench/dut/EXMEM/out8
add wave -noupdate -format Literal /cpu5_testbench/dut/MEMWB/in1
add wave -noupdate -format Literal /cpu5_testbench/dut/MEMWB/in2
add wave -noupdate -format Literal /cpu5_testbench/dut/MEMWB/in4
add wave -noupdate -format Logic /cpu5_testbench/dut/MEMWB/clk
add wave -noupdate -format Logic /cpu5_testbench/dut/MEMWB/in3
add wave -noupdate -format Literal /cpu5_testbench/dut/MEMWB/out1
add wave -noupdate -format Literal /cpu5_testbench/dut/MEMWB/out2
add wave -noupdate -format Literal /cpu5_testbench/dut/MEMWB/out4
add wave -noupdate -format Logic /cpu5_testbench/dut/MEMWB/out3
add wave -noupdate -format Literal /cpu5_testbench/dut/memtoreg_mux/in1
add wave -noupdate -format Literal /cpu5_testbench/dut/memtoreg_mux/in2
add wave -noupdate -format Literal /cpu5_testbench/dut/memtoreg_mux/out
add wave -noupdate -format Logic /cpu5_testbench/dut/memtoreg_mux/sel
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {483338 ps} 0}
configure wave -namecolwidth 360
configure wave -valuecolwidth 213
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {470845 ps} {512061 ps}
